A very bright and hopeful news for all those who are very depressed of being bald at a very young age !
http://www.bbc.co.uk/news/health-17457098
So cheer up and good luck ! :)
Say bye bye to baldness - hopefully :)
A very bright and hopeful news for all those who are very depressed of being bald at a very young age !
http://www.bbc.co.uk/news/health-17457098
So cheer up and good luck ! :)
polling in 8085 microprocessor
What do you mean by polling in 8085.
When the microprocessor receives an Interrupt Service Request (ISR) on the interrupt line it must determine which of the devices connected to that input sent the request.
Software Polling is one method by which it can do so.
In Software Polling:
A software routine is used to identify the device requesting service. It does so by checking each device to see if it was the one needing service.
hardware interrupts in 8085 microprocessor
Explain hardware interrupts in 8085.
• When a device interrupts, it actually wants the MP to give a service which is equivalent to asking the MP to call a subroutine. This subroutine is called ISR (Interrupt Service Routine)
• Interrupts:
• The 8085 microprocessor has 5 interrupts. They are presented below in the order of their priority (from lowest to highest):
• INTR is mask able 8080Acompatible interrupt. When the interrupt occurs the processor fetches from the bus one instruction.
• RST5.5 is a mask able interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 2Ch (hexadecimal) address.
• RST6.5 is a mask able interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 34Ch (hexadecimal) address.
• RST7.5 is a mask able interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 3Ch (hexadecimal) address.
• Trap is a non-maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 24h (hexadecimal) address.
• All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled individually using SIM instruction.
• When a device interrupts, it actually wants the MP to give a service which is equivalent to asking the MP to call a subroutine. This subroutine is called ISR (Interrupt Service Routine)
• Interrupts:
• The 8085 microprocessor has 5 interrupts. They are presented below in the order of their priority (from lowest to highest):
• INTR is mask able 8080Acompatible interrupt. When the interrupt occurs the processor fetches from the bus one instruction.
• RST5.5 is a mask able interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 2Ch (hexadecimal) address.
• RST6.5 is a mask able interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 34Ch (hexadecimal) address.
• RST7.5 is a mask able interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 3Ch (hexadecimal) address.
• Trap is a non-maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 24h (hexadecimal) address.
• All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled individually using SIM instruction.
Memory Mapping Scheme
What is the memory mapping scheme? Give any one advantage and disadvantage.
MEMORY MAPPING SCHEME:
WEB MAPPING:
Web mapping is the process of designing, implementing, generating and delivering maps on the World Wide Web and its product.
ADVANTAGE & DISADVANTAGE:
While web mapping primarily deals with technological issues, web cartography additionally studies theoretic aspects: the use of web maps, the evaluation and optimization of techniques and workflows, the usability of web maps, social aspects, and more.
Web maps can easily deliver up to date information. If maps are generated automatically from databases, they can display information in almost realtime. They don't need to be printed, mastered and distributed.
Reliability issues – the reliability of the internet and web server infrastructure is not yet good enough. Especially if a web map relies on external, distributed data sources, the original author often cannot guarantee the availability of the information.
Definitions of (a) Instruction Cycle (b) M/c cycle (c) T-state
Define: (a) Instruction Cycle (b) M/c cycle (c) T-state.
Instruction Cycle:
The time period during which one instruction is fetched from memory and executed when a computer is given an instruction in machine language. There are typically four stages of an instruction cycle that the CPU carries out:
1. Fetch the instruction from memory. This step brings the instruction into the instruction register, a circuit that holds the instruction so that it can be decoded and executed.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an indirect address.
4. Execute the instruction.
M/C CYCLE:
The processor cycle or machine cycle is the basic operation performed by the processor. To execute an instruction, the processor will run one or more machine cycles in a particular order.
T-state:
For any instruction cycle, Opcode fetch is the first machine cycle. We know that each machine cycle may have 3 to 6 T-states. This Opcode fetch machine cycle consists of 4 T-states.
T1 State:
During the T1 state, the contents of the program counter are placed on the 16 bit address bus.
T2 State:
opcode is placed on D0-D7 of the Address/Data bus.
T3 State:
the Opcode of the A/D bus is transferred to the instruction register of the microprocessor.
T4 State:
In this state the Opcode which was fetched from the memory is decoded.
List four interrupts of 8085 microprocessor
List four interrupts of 8085.
INTERRUPTS OF 8085
- INTR,
- RST7.5
- RST6.5
- RST5.5